MIPS ISAs before "Revision 6" do not support third operand for the rdhwr instruction. But LLVM generates three-operands version of the instruction on any MIPS64 ISAs. This is regression caused by r335162. % cat test.ll declare i8* @llvm.thread.pointer() nounwind readnone define i8* @thread_pointer() { %1 = tail call i8* @llvm.thread.pointer() ret i8* %1 } % llc -march=mips64 < test.ll ... rdhwr $3, $29, 0 % llc -march=mips < test.ll ... rdhwr $3, $29
Fixed at r341919. https://reviews.llvm.org/rL341919
This affects the release_70 branch; could it please be cherry-picked?
yeah, we should back port it. I have been affected by this in the debian packaging.
Sure. I'm going to send request on backporting this and some other MIPS-related commits soon.